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PM8352A OctalPHY® 1G
8 Channel 933 Mbit/s - 1.25 Gbit/s Multi-Protocol SERDES
Note: The letter A was added to the product number when the manufacturer changed. Documents written prior to the manufacturer change remain valid.
Documents for the PM8352A
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Symbols/Footprints
Features
GENERAL
- Eight independent 933 Mbit/s to 1.25 Gbit/s IEEE 802.3-2000 Gigabit Ethernet compliant and ANSI X3T11 Fibre Channel System compatible transceivers.
- Configurable as eight independent channels or configurable as a single logical trunked channel with deskew providing 16 Gbit/s duplex data rate.
- Integrated clock synthesis, clock recovery, serializer/deserializer, and 8B/10B encode/decode logic.
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- IEEE 802.3-2000 Gigabit Ethernet Physical Coding Sublayer (PCS) logic.
- Minimal external components required.
- Two wire IEEE 802.3 MDC/MDIO serial port for configuration and status.
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SERIAL INTERFACE
- High-speed outputs feature programmable output current to optimize drive distance and power - directly drives 50 Ω (100 Ω differential) systems.
- On-chip termination to directly drive dualterminated 50 Ω traces.
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- Direct AC coupled interface to copper serial backplanes, optics and coaxial cable.
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PARALLEL INTERFACE
- Dual Data Rate (DDR) parallel interface with synchronous receive clock (clock
forwarding) -- halves interfacing logic terminal count.
- Byte Interleaved or Nibble mode parallel interface.
- Supports GMII and TBI (Ten-bit Interface) standards.
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- Receive channel output clocks eliminate the need for PLLs in interface ASICs.
- 1.8 V and 2.5 V interoperable; 3.3 V tolerant.
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TEST FEATURES
- Provides a standard IEEE 1149.1 JTAG test port for boundary scan board test purposes.
- Built-in self-test (BIST) via internal packet generator/checker.
- Extensive control of loopback, BIST and operating modes via 802.3 compliant MDC/MDIO serial interface.
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- Per-channel control of serial and parallel loopbacks.
- Built-in 8B/10B error counters.
- An evaluation kit (PM2375-KIT) is available for the OctalPHY 1G.
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PHYSICAL
- Ultra-low power operation using 0.18 µ CMOS technology.
- Thermally enhanced, 289-pin, 19 mm x 19 mm CABGA package.
- 1.8 V core and analog power.
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- I/O voltage configurable as 2.5 V or 1.8 V.
- Designed to operate over a wide temperature range and is suited for central office and outside plant equipment.
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Applications
- High-speed serial backplanes.
- IEEE 802.3-2000 Gigabit Ethernet dense line cards.
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- ANSI X3T11 Fibre Channel dense line cards.
- Link Aggregation.
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PMC-2041434 PM8352A OctalPHY 1G 289 CABGA CAD Symbols and Footprints [193 KB]