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PM7348 S/UNI® IMA 4
S/UNI INVERSE MULTIPLEXING FOR ATM, 4 LINKS
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Features
IMA
- IMA 1.1 protocol including group and link state machines implemented by on-chip hardware. All ICP cell processing is performed internally by the S/UNI IMA device with no requirement for microprocessor intervention; however, ICP cells are made available for diagnostic purposes.
- Supports up to 4 simultaneous IMA groups.
- Each IMA group can support any number of supported links.
- Each link can be programmed for either IMA processing or cell delineation.
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- Supports all IMA Group Symmetry modes:
- Symmetrical configuration with symmetrical operation.
- Symmetrical configuration with asymmetrical operation.
- Asymmetrical configuration with asymmetrical operation.
- Performs IMA differential delay calculation and synchronization. Provides programmable limit on differential delay tolerance and minimum number of links per group.
- Supports up to 282 ms (for T1 links) and 226 ms (for E1 links) link-differential delay among links in an IMA group.
- Performs ICP and stuff-cell insertion and removal.
- Supports both Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) transmit ICP stuffing modes.
- Supports IMA frame lengths (M) equal to 32, 64, 128, or 256.
- Optionally supports the IMA 1.0 method of reporting Rx cell information as defined in appendix C.8 of the ATM Forum Inverse Multiplexing for ATM Specification Version 1.1 for symmetrical configurations; also optionally supports the IMA 1.1 method of reporting Rx cell information when sending and receiving the IMA 1.0 OAM Label.
- Provides IMA layer statistic counts and alarms for support of IMA Performance and Failure Alarm Monitoring and MIB support.
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- Provides per link counters for statistics and performance monitoring:
- ICP Violations.
- OIF anomalies.
- Rx Link stuff events.
- Tx Link stuff events.
- User cells.
- Filler cells.
- Provides per group counters for statistics and performance monitoring:
- User cells received.
- Filler cells received.
- User cells transmitted.
- Filler cells transmitted.
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TC FEATURES
- Performs cell delineation on all links.
- Performs receive cell Header Error Check (HEC) checking and transmit cell HEC generation.
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- Optionally supports receive cell payload unscrambling and transmit cell payload scrambling.
- Provides TC layer statistics counts and alarms for MIB support.
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INTERFACE SUPPORT
- Clock/Data Interface:
- Supports 4 individual serial (T1 or E1 or unchannelized rates up to 8 Mbps) links via a 2-pin line interface.
- Supports ATM over fractional T1/E1 by providing the capability to select any DS0 timeslots that are active in a link.
- Serial link interface supports both independent transmit clock (ITC) and common transmit clock (CTC) options.
- Interfaces to a 1M x 16 SDRAM (16 Mbits of storage for 282 msec of T1, 226 msec of E1 differential delay tolerance) through a 16-bit SDRAM interface. Note that other larger SDRAM sizes can also be supported to support future market availability.
- Provides a 16-bit microprocessor bus interface for configuration and Link and Unit Management.
- ATM receive interface supports 8- and 16-bit UTOPIA L2 or Any-PHY cell interfaces at clock rates up to 52 MHz.
- Any-PHY receive slave appears as single device.
- The PHY-ID of each cell is identified in the in-band address.
- UTOPIA L2 receive slave appears as a 4 port multi-PHY.
- UTOPIA L2 receive slave can also appear as a single port with the logical port provided as a prepend or in the HEC/UDF field.
- ATM transmit interface supports 8- and 16-bit UTOPIA L2 and Any-PHY cell interfaces at clock rates up to 52 MHz.
- Each link configured for cell delineation or each IMA group appears as a PHY port on the Any-PHY and UTOPIA L2 bus.
- Any-PHY transmit slave appears as an 4-port multi-PHY.
- The PHY-ID of each cell is identified in the in-band address.
- UTOPIA L2 transmit slave appears as an 4-port multi-PHY.
- Seamlessly interconnects to PMC-Sierra's PM7326 S/UNI APEX ATM/Packet Traffic Manager and Switch and PM7324 S/UNI ATLAS ATM layer devices.
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LOOPBACK AND DIAGNOSTIC FEATURES
- Supports UTOPIA L2 / Any-PHY Loopback (global loopback where all cells received on the UTOPIA L2 / Any-PHY interface are looped back out).
- Supports Line Side Loopback (global loopback where all data received on the line side is looped back out).
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- Supports the capability to trace ICP cells for any group.
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SOFTWARE
- The S/UNI IMA device driver, written in ANSI C, provides a well-defined Application Programming Interface (API) for use by application software. Low level utility functions are also provided for diagnostics and debugging purposes. Software wrappers are used for RTOS-related functions making the S/UNI IMA device driver portable to any Real Time Operating System (RTOS) and hardware environment. The S/UNI IMA device driver is compatible across the S/UNI IMA family of devices.
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PACKAGING
- Implemented in low power, 0.18 micron, 1.8V CMOS technology with TTL compatible inputs and outputs.
- Provides a standard 5-pin P1149 JTAG port.
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- 324 ball PBGA, 23mm x 23mm.
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Applications
- Integrated Access Device (IAD).
- Digital Subscriber Loop Access Multiplexers (DSLAMs).
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- Wireless Base Transceiver Stations.
- Customer Premise Equipment (CPE).
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