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PM5422 META 20G - Dual 10 Gbit/s Carrier Ethernet Physical
Layer Device for 10GE, OTN, and POS
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Features
Product Overview
The PM5422 META 20G is a feature-rich, high capacity, single chip
solution that provides two universal 10 Gbps interfaces for Service
Provider Routers, Carrier Ethernet Switches, Enterprise WAN, and
Packet Optical Transport Platforms (P-OTPs). Designed with flexibility
in mind, the META 20G offers the industry's first truly
universal solution for 10 Gbps interfaces.
Each 10 Gbps port may be configured to carry 10GE-LAN, 10GE-WAN,
OTU2, or OC-192c/STM-64c (Packet over SONET/SDH) rate
signals.
The META 20G provides an array of packet mapping options
needed by Router and Carrier Ethernet Switch line cards. The
META 20G supports GFP multiplexing of up to 64 Ethernet (VLAN
tagged and non-tagged) and IP/MPLS data streams into an OTU2.
10GE-LAN/WAN may also be mapped into an OTU2 in accordance
with ITU G.709/G.sup43. Dual 10GE MAC/PCS and HDLC/PPP
processors deliver a future-proof, line-card solution.
The META 20G provides OEMs with an industry leading solution
for Carrier Ethernet applications. Packet-based timing distribution
via Synchronous Ethernet and IEEE 1588v2 (Precision Timing
Protocol) is provided, along with 802.3ah Link OAM. Integrated
support of these features enables the widespread adoption of
Carrier Ethernet.
Benefits
- Dramatic Reduction in Capital and Operating Expenditure:
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Universal 10G ports enables a single line card to service
multiple line-card applications, reducing development and
inventory costs for equipment manufacturers and service
providers
- OTN's Simplified Operation, Administration, and
Maintenance (OAM) reduces the operational network cost
- Carrier Ethernet Ready
- Robust timing recovery and distribution with integrated
SyncE and IEEE 1588v2/PTP timing support
- Integrated support for IEEE 802.3ah Link OAM
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Optimal Footprint and System Design Flexibility
- Integrated Carrier Ethernet features eliminate the need for
external processors
- Universal port flexibility reduces power and space consumption versus comparable
multi-device solutions
- Single 155.52 MHz clock operation reduces BOM costs
- Glueless interconnect to system side next generation packet
platforms via Interlaken, XAUI, and extended XAUI as well
as high-density line side XFP and SFP+(limiting) optics
modules
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Product Highlights
Universal Port Flexibility
- Dual 10 Gbps line interfaces independently configurable for
OTU2, 10GE-LAN, 10GE-WAN, or SONET/SDH OC-192c/STM-64c
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- Glueless interface to XFP or SFP+ (Limiting) optics modules
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OTN Subsystem
- OTU2 framer
- ITU-T G.709, ITU-T G.798 and ITU-T G.975 compliance
- Flexible OTU, ODU and OPU overhead/data processing and frame
alignment
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- Up to six levels of Tandem Connection Monitoring (TCM)
- Independent performance counters for the accumulation of
BIP-8 BEI and other error conditions with optional interrupts
- Access to full overhead via internal registers and PCIe accessible
RAM
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Flexible Packet Mapping into OTN and SONET/SDH
- Maps a wide variety of protocols into OTN and SONET/SDH
- Encapsulates packet streams into ITU-T G.7041 GFP-F, HDLC, LAPS
or PPP
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- Supports GFP multiplexing of data streams into ODU2
- Includes 10GE mapping into OTN, compliant with ITU G.Sup43 6.1,
6.2, 7.1, 7.2 and 7.3
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Ethernet Subsystem
- Integrated IEEE 802.3 compliant media access controllers (MAC)
- Integrated 10GE WAN Interface sublayer (WIS) framing and
descrambling
- 64B/66B physical coding sub-layer (PCS) for 10GE
- Lossless IEEE 802.3 local flow-control with integrated packet
buffers
- Comprehensive per-port Ethernet statistics
- Frame delineation and generation with configurable IPG,
preamble, and CRC
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- Transparent transmission of VLAN tagged Ethernet frames
- Frame sizes of 64 bytes to 9.6 Kbytes
- Dynamic programmable depth full-packet store-and-forward
buffers for burst tolerance and rate adaptation
- Transmit and receive of IEEE 802.3ah Link OAM, LACP, and
Management VLAN messages
- Ethernet management port allows external processing of LACP
PDUs, Management VLAN, or OAM packets
- On-chip packet buffer
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Ethernet Timing Synchronization
- Performs packet-based timing recovery and distribution as well as
time-of-day (TOD) recovery and distribution
- Implements per-port Ethernet Link OAM & Timing using an
integrated 32-bit MIPS4K CPU
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- Implements firmware-based link OAM defined by IEEE 802.3ah
- Contains per-port Synchronous Ethernet & Precision Timing
Protocol (PTP) IEEE 1588v2 protocols
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GFP and HDLC/PPP Packet Processors
- Two integrated GFP-F processors, each supporting 64 channels
- Two channels of HDLC/PPP/LAPS processing
- GFP multiplexing support, allowing multiple packet flows such as IP
or MPLS to be mapped into the same ODU2
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- GFP frame filtering with configurable disposition
- Fully programmable GFP and HDLC/PPP header generation
- Flexible insertion and extraction of GFP client management frames
and PPP Control Frames. In addition supports flow-through of PPP
Control Frames to the Packet Interface
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Packet Interface
- Interlaken v1.1 interface
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SONET/SDH Framing and Mapping Support
- OC-192c SONET and STM-64 AU-4-64c SDH framing
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- High-order pointer and overhead processing
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PCI Express Microprocessor Interface
- PCIe version 1.1 compliant
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Applications
- Metro and Core Router Multi-Protocol Line cards
- Datacenter Switch uplinks
- Layer 2 Packet OTPs
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- xPON OLT interfaces
- DSLAM transport cards
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PMC-2100054 
