- Maps/extracts up to twelve channels of DS3/E3 serial data streams into/from an STS-1/STM-0 SPE using either AU-3 or TUG-3/AU-4 mapping/demapping.
- Digitally synchronizes/desynchronizes DS3/E3 serial streams to/from SONET/SDH payloads, accommodating plesiochronous timing offsets between the line and system timing references, through appropriate processing of bit stuffing and pointer movements.
- Provides automatic fast-lock mechanism for desynchronizing DS3/E3 serial streams from SONET/SDH payloads.
- Configurable on a per channel basis for serial data streams at two of the following line rates at any given time:
- DS3 (44.736 Mbit/s)
- E3 (34.368 Mbit/s)
- STS-1E (51.84 Mbit/s)
- Fully compliant to all ITU and ANSI DS3/E3 mapping/demapping jitter specifications.
- Provides twelve on-chip DS3 and E3 (G.751 and G.832) framers in both receive and transmit directions for bi-directional performance monitoring purposes.
- Provides twelve on-chip STS-1E (EC-1) framers for SONET Section, Line, and Path overhead termination.
- Provides termination for SONET Section, Line, and Path overhead or SDH Regenerator Section, Multiplexer Section, and High Order Path overhead for STS-12/STM-4.
- Configurable up to six channels of DS3 or E3 serial streams mapped/demapped into/from STS-1E (EC-1) serial streams.
- Provides duplex 77.76 MHz 8-bit wide ingress and egress parallel TelecomBus line side compatible interfaces. Can be combined with up to three other ARROW-12xETEC devices to form a 32-bit 77.76MHz STS-48/STM-16 TelecomBus compatible interface.
- Provides a limited STS-1/AU-3 or TUG3/AU-4 time slot interchange function to interchange or groom paths on the TelecomBus or serializerdeserializer interfaces.
- Provides a duplex 8-bit 77.76 MHz STS-12/STM-4 line side interface for direct connection to external clock recovery, clock synthesis, and serializer-deserializer components.
- Provides frame synchronization/insertion for M23 or C-bit parity DS3 applications, alarm detection/insertion; and accumulates line code violations, framing errors, parity errors, path parity errors, FEBE events along with diagnostic features. In addition, far end alarm channel codes may be detected/inserted and an integral HDLC receiver is provided to terminate/insert the path maintenance data link.
|
- Provides frame synchronization for G.751 or G.832 E3 applications, alarm detection/insertion; and accumulates line code violations, framing errors, parity errors, FEBE events along with diagnostic features. In addition, in G.832, the Trail Trace is detected/inserted and an integral HDLC receiver is provided to terminate/insert either the Network Requirement or the General Purpose data link.
- Provides capabilities to feed PDH alarm events forward into the SONET/SDH alarm hierarchy and vice versa.
- Provides dedicated pins to extract to and insert from the entire SONET/SDH overhead. The overhead bytes may be sourced from internal registers or from the bit serial overhead input stream. Overhead insertion may also be disabled.
- Extracts and serializes, on dedicated pins, the data communication channels (D1-D3 or D4-D12) and inserts the corresponding signals into the transmit stream.
- Extracts and filters the automatic protection switch (APS) channel (K1, K2) bytes into internal registers. Inserts the APS channel into the transmit stream.
- Provides integral transmit data link and receive data link HDLC controllers with 128-byte FIFO depths for the STS-12 section and line overhead.
- Provides per channel performancemonitoring counters suitable for accumulation periods of up to 1 second.
- Provides per channel programmable pseudo-random test pattern generation, detection, and analysis features.
- Provides diagnostic line and payload loopbacks for DS3/E3/STS-1E (EC-1) and SONET/SDH.
- Provides a 16-bit microprocessor interface for configuration, control, and status monitoring.
- Provides a standard 5-signal P1149.1 JTAG test port for boundary scan board test purposes.
- Low power 3.3 V / 1.8 V CMOS technology with 5 V tolerant inputs.
- Industrial Temperature Operating Range (-40 °C to +85 °C).
- Available in a high-density 580-pin TSBGA package (35 mm x 35 mm) with 1 mm ball pitch.
|
