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PM5384 S/UNI® 1x155

Documents

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Version Issue Date

Product Brief

PDFS/UNI-1x155 Single Channel OC-3c ATM and POS Physical Layer Device Short Form Data Sheet [47 kB] PMC-2011690 2  2003-12-31 

Data Sheet

Locked Document, Log In RequiredPDFS/UNI-1x155 Telecom Standard Product Data Sheet [2.26 MB] PMC-2010300 5  2011-02-02 

Errata

Locked Document, Log In RequiredPDFS/UNI-1x155 DATA SHEET ERRATA FOR REVISION B [99 KB] PMC-2020123 8  2011-10-27 

Software Documentation

Locked Document, Log In RequiredPDFS/UNI-1x155 Device Driver Manual [777 kB] PMC-2012633 2  2002-04-05 

Software

Locked Document, Log In RequiredPDFS/UNI-1x155 Device Driver [150 kB] PMC-2012583 rel 1.0  2002-03-27 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5384 S/UNI-1x155 [443 kB] PMC-2020348   2003-10-06 
Locked Document, Log In RequiredPDFS/UNI-1x155 Configuration Guide Application Note [141 kB] PMC-2012406 3  2003-06-27 
Locked Document, Log In RequiredPDFS/UNI-1x155 Design Guidelines Application Note [154 kB] PMC-2012407 1  2001-11-23 

Models

Locked Document, Log In RequiredPDFPM5384 SUNI-1x155 [17 kB] 1.01  2002-10-08 
Locked Document, Log In RequiredPDFINPUT OUTPUT BUFFER INFORMATION SPECIFICATION (IBIS) MODEL FOR THE PM5384 SUNI 1X155 [17 kB] PMC-2012656 1  2001-12-19 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM5384 Device PMC-2020212 1  2002-02-11 

Features

  • Single chip ATM and Packet over SONET/SDH Physical Layer Device operating at 155.52 Mbit/s.
  • Implements the ATM Forum User Network Interface (UNI) and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
  • Implements Point-to-Point Protocol (PPP) over SONET/SDH according to RFC 2615.
  • Processes duplex bit-serial 155.52 Mbit/s STS-3c/STM-1 data streams with on-chip clock and data recovery and clock synthesis.
  • Complies with Bellcore GR-253-CORE (1995 Issue) jitter tolerance, jitter transfer and intrinsic jitter criteria.
  • Provides control circuitry required to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
  • Provides a UTOPIA Level 2, 8-bit wide system interface (clocked up to 52 MHz) with parity support for ATM applications.
  • Provides a UTOPIA Level 2, 16-bit wide system interface (clocked up to 52 MHz) with parity support for ATM applications.
  • Provides a SATURN POS-PHY Level 2, 16-bit system interface (clocked up to 52 MHz) for Packet over SONET/SDH (POS) applications (similar to UTOPIA Level 2, but adapted for packet transfer).
  • Provides support functions for 1+1 APS operation.

GENERAL
  • Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
  • Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring.
  • Low power 2.5/3.3 V CMOS with 5 V TTL-compatible digital inputs/outputs (PECL inputs/outputs are 3.3 V and 5 V compatible).
  • Industrial temperature range (-40°C to +85°C).
  • 15 mm x 15 mm 196 pin stPBGA package with 1 mm ball pitch.

Applications

  • Routers and Layer 3 Switches.
  • 3G Wireless Base Station Controllers.
  • DSLAM Uplinks.
  • WAN and Edge ATM switches.
  • LAN switches and hubs.
  • Packet switches and hubs.
  • Network Interface Cards and Uplinks.
 
 
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