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PM5336 ARROW 2488
High-Capacity Single-Chip Add/Drop Multiplexer

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Version Issue Date

Product Brief

Locked Document, Log In RequiredPDFPM5336 ARROW 2488 High-Capacity Single-Chip Add/Drop Multiplexer Product Brief [208 KB] PMC-2052398 2007-08-17 

Application Note

Locked Document, Log In RequiredPDFAttaching Passive Heat Sinks to Organic Flip Chip Packages [142 KB] PMC-2020246 2007-05-02 

White Papers

Locked Document, Log In RequiredPDFAn Introduction to Transport Networks for Telecommunications [384 KB] PMC-2050808 2005-07-20 
Locked Document, Log In RequiredPDFA Tutorial on SONET/SDH Automatic Protection Switching (APS) [353 KB] PMC-2050248 2005-02-15 
Locked Document, Log In RequiredPDFA Tutorial on SONET/SDH [819 KB] PMC-2030895 2005-03-23 
Locked Document, Log In RequiredPDFApplication of Message Assisted Protection Switching (MAPS) to APS Architectures [402 KB] PMC-2021902 2003-09-22 

Symbols/Footprints

  Version Issue Date
Locked Document, Log In RequiredZipped FilePMC-2061981 PM5336 ARROW 2488 1152 FCBGA CAD Symbols and Footprints [565 KB]22007-02-02

Features

GENERAL

The PM5336 ARROW 2488 device is a feature-rich, high capacity single-chip solution that enables optimized compact MSPPs and highly integrated central cross-connects or high fan-in tributary cards for chassis-based MSPPs, packet MSPPs, and ROADMs. The ARROW 2488 enables low chip count and power-efficient equipment designs with unprecedented scalability and carrier-grade reliability.

The ARROW 2488 consists of a SONET/SDH network interface and framer with integrated SERDES including full section, line, and high-order path processors, non-blocking memory-based high-order STS/AU and low-order VT/TU cross-connect, low-order VT/TU path processors, and a large number of expansion interfaces (both ESSI serial links and a Parallel TelecomBus interface). The SONET/SDH framer, high-order cross-connect, and low-order cross-connect support Message Assisted Protection Switching (MAPSTM), a mechanism that allows standards-based protection switching without software intervention.

BENEFITS

  • Optimizes compact multi-port OC-48/STM-16 architectures, while allowing scalability to multi-port OC-192/STM-64 applications
  • Integrates field-proven CHESSTM intellectual property, reducing development cycles through reuse of CHESS software base
  • Exceeds the requirement for 50 msec protection switching for up to 5376 tributaries using a fully hardware-based APS algorithm (MAPS)

SONET/SDH NETWORK INTERFACE AND FRAMER (ARROW)

  • Two groups of four SONET/SDH interfaces, each supporting two modes of operation:
    • Quad OC-12/3/STM-4/1 mode (four interfaces operating at 622.08 Mbit/s or 155.52 Mbit/s, selectable per port)
    • Single OC-48/STM-16 mode (one interface operating at 2488.32 Mbit/s)
  • CML compatible serial interfaces to connect to optical transceivers
  • Framing, high order pointer processing, alarm processing and overhead processing on all received network streams
  • Dedicated pins to extract/reinsert B3/N1 path overhead bytes for Tandem Connection Monitoring
  • Per-framer connection ID message, allowing verification of high order path connectivity across single or multistage fabrics
  • BLSR and MSSPRing protection switching with alarm processing, K-byte express, automatic payload configuration, and other features
  • Insertion/extraction of transport overhead (TO) bytes from the line side interface

STS/AU INTELLIGENT CROSS-CONNECT (TSE)

  • High capacity, memory-based, HO cross-connect capable of switching at STS-1/AU-3 granularity
  • Floating delay management
  • One 32-bit or four 8-bit 77.76 MHz TelecomBus interfaces connecting to parallel TelecomBus framers and mappers
  • Cross-connect implements HO MAPS algorithm to extract, filter and interpret line status code on a per STS-1 basis
  • TOH byte insertion and extraction (99 TOH bytes per port)
  • Support for a set of active and standby configuration memory pages, permitting new switch settings to be updated in one page while the TSE operates from the control settings of the other page
  • 2.5 Gbit/s to/from 622 Mbit/s interleaving/de-interleaving
  • Muxing scheme enables different port asset allocations for different applications

SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR (TUPP)

  • Configurable, multi-channel, payload processor that aligns and monitors performance of the SONET virtual tributaries (VTs) or the SDH tributary units (TUs)
  • Optionally monitors and terminates the path overhead of any legal mix of HO payloads in a SONET/SDH stream
  • Remaps the incoming transport frame, payload frame and tributary multi-frame alignment on the Receive side to the VT/TU Cross- Connect (WSE) frame and multi-frame alignments through low order pointer processing
  • Drop/Add path of TUPP supports multiple SDH payload conversions

VT/TU INTELLIGENT CROSS-CONNECT (WSE)

  • Memory-based, LO cross-connect capable of switching at VT/TU granularity
  • Accepts and switches SONET VT and SDH TU streams.
    • All SONET virtual tributary types (VT1.5, VT2, VT3, and VT6)
    • All LO SDH tributary unit types (TU11, TU12, TU2, and TU3)
  • Support for a set of active and standby configuration memory pages, permitting new switch settings to be updated in one page while the WSE operates from the control settings of the other page
  • Cross connect implements the Low Order MAPS algorithm to extract, filter, and interpret the line status code on a per VT/TU basis

INTERFACES

  • ESSI links running at 2.488Gbit/s or 622Mbit/s (selectable per link)
  • Optional differential clock output in 622 Mbit/s mode for interconnect to FPGAs with no clock recovery
  • SONET/SDH B3/N1 path overhead interface for Tandem Connection Monitoring
  • SONET/SDH HO (STS/AU) transport overhead interface
  • SONET/SDH ring control/alarm port
  • Parallel TelecomBus interface with two functional modes:
    • Single STS-48/STM-16 mode supporting a 77.76 MHz 32-bit TelecomBus interface
    • Quad STS-12/STM-4 mode supporting four independent 77.76 MHz 8-bit TelecomBus interfaces
  • Standard P1149.1 JTAG test port for boundary scan
  • 32-bit microprocessor interface for status monitoring and configuration

PACKAGE

  • 35x35mm 1152-balls FCBGA
 

Applications

  • Multi-port OC-48/STM-16 single-chip solution for compact MSPPs
  • High fan-in, multi-rate SONET/SDH front-end for line cards for MSPPs, packet MSPPs, and ROADMs
  • Centralized high-order and/or low-order cross-connect and pointer processor (with optional network interfaces) for chassis-based optical platforms
  • One-armed low-order cross-connect and pointer processor for MSPPs
 
 
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