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PM3393 S/UNI® 1x10GE XP
Single Chip 10 Gigabit Ethernet LAN PHY For XAUI-Based Optics
Documents
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Symbols/Footprints
Please contact apps@pmc-sierra.com to gain access to the following
design support documents for PM3393 (S/UNI 1x10GE XP)
| Document Number |
Document Name |
| PMC-2030012
| S/UNI-1x10GE-XP Device Errata Revision A
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| PMC-2021403
| PM3393 S/UNI-1x10GE-XP Reference Design
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| PMC-2022196
| S/UNI-1x10GE XP Device Driver
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| PMC-2030333
| PM3393 S/UNI-1x10GE-XP Configuration Guide
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| NA
| S/UNI 1x10GE-XP Reference Design Schematics
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| PMC-2010750
| Signal Integrity for PMC-Sierra 3.125/2.488/1.5GBPS Links
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| PMC-2011362
| Chess-II Thermal Management Considerations
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| PMC-2021027
| BSDL File for S/UNI 1x10GE-XP
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The customer support website also gives you access to a number of useful SPI4.2 (PL4) Application Notes
Features
- Implements 10 Gigabit LAN PHY according the IEEE 802.3ae standard.
- Provides direct connection to XENPAK optical modules via a 4-bit by 3.125 Gbit/s IEEE 802.3ae XAUI line-side interface.
- Provides SATURN® POS-PHY™ Level 4 16-bit LVDS System-side Interface (clocked at 700 MHz nominal).
- Provides an auxillary XAUI interface to protect against optical failure.
- Provides extract and insert ports for ethernet preamble bytes to support ethernet-based OAM protocols and carry user-defined information.
- Provides standard IEEE 802.3ae 10 Gigabit Ethernet Media Access Controller (10GMAC) for frame verification.
- Implements IEEE 802.3ae 10GBase-X Physical Coding Sub-layer (PCS).
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- Provides internal FIFOs (64 Kbyte ingress and 16 Kbyte egress) to accommodate system latencies and provide loss-less flow control for up to 2 Km for regular size frames.
- Provides line-side and system-side loopbacks for system level diagnostic capability.
- Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring.
- Standard 5 signal P1149.1 JTAG test port.
- Low power 1.8 V CMOS core logic with 3.3 V CMOS/TTL compatible digital inputs and digital outputs.
- Industrial temperature range (-40 °C to +85 °C).
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10 GIGABIT ETHERNET MAC
- Verifies frame integrity (FCS and length checks).
- Provides egress Ethernet frame encapsulation (pads to min. size, add preamble, IFG and CRC generation).
- Supports VLAN tagged frames.
- Provides eight exact-match address filters to filter frames based on SA, DA, or VID.
- Provides 64-bin hash based algorithm to filter multicast addresses.
- Minimum frame size of 64 bytes.
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- Provides statistics counters to support RMON/SNMP.
- Supports jumbo frames up to 9.6 Kbytes.
- Programmable inter-packet gap (IPG).
- Implements in-band PAUSE flowcontrol and provides support for out-ofband flow control.
- Upper layer device can flow-control using dedicated pins or host signaling to cause generation of a PAUSE frame.
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DEVICE INTERWORKING
- Other PMC-Sierra devices that implement the POS-PHY Level 4 interface include:
- S/UNI 1x10GE.
- S/UNI 9953.
- S/UNI 9953 POS.
- S/UNI 10xGE.
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POS-PHY LEVEL 4 INTERFACE
- Designed to transmit cells, packets or frames between physical and data-link layer devices.
- Requires less pins and draws less power than other 10 Gigabit interface options.
- Compliant with the following standards:
- Optical Internetworking Forum – System Physical Interface Level 4 Phase 2 (SPI-4 P2 and associated specification OIF-SPI4.02.0).
- SATURN POS-PHY Level 4, Issue 6, March 2001.
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Applications
- Edge and Core Routers.
- Multi-Service (Multi-Protocol) Switches.
- Internet POP and Transport POP L2 Ethernet Switches.
- Data cards for Multi-service Provisioning Platforms
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- Optical cross-connects.
- 10 Gigabit Ethernet Enterprise Switches with XENPAK uplinks.
- 10 Gigabit Ethernet test equipment.
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PMC-2051575 PM3393-FI S/UNI 1x10-XP 672 FCBGA CAD Symbols and Footprints [376 KB]